orthogonal instruction set - определение. Что такое orthogonal instruction set
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Что (кто) такое orthogonal instruction set - определение

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orthogonal instruction set         
<architecture> An instruction set where all (or most) instructions have the same format and all registers and addressing modes can be used interchangeably - the choices of op code, register, and addressing mode are mutually independent (loosely speaking, the choices are "orthogonal"). This contrasts with some early Intel microprocessors where only certain registers could be used by certain instructions. Examples include the PDP-11, 680x0, ARM, VAX. (2002-06-26)
Orthogonal instruction set         
In computer engineering, an orthogonal instruction set is an instruction set architecture where all instruction types can use all addressing modes. It is "orthogonal" in the sense that the instruction type and the addressing mode vary independently.
Reduced Instruction Set Computer         
  • An IBM [[PowerPC 601]] RISC microprocessor
  • RISC-V prototype chip (2013).
PROCESSOR EXECUTING ONE INSTRUCTION IN MINIMAL CLOCK CYCLES
Reduced Instruction Set Computer; RISC processor; Reduced Instruction Set Code; Reduced Instruction Set Computing; RISC; RISC-based; RISC-based system; RISC System/6000 SP; Reduced instruction set; RISC architectures; RISC instruction set; RISC-based computer design approach; RISC principles; Reduced instruction set computing
<processor> (RISC) A processor whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a Complex Instruction Set Computer). Features which are generally found in RISC designs are uniform instruction encoding (e.g. the op-code is always in the same bit positions in each instruction which is always one word long), which allows faster decoding; a homogenous {register set}, allowing any register to be used in any context and simplifying compiler design; and simple addressing modes with more complex modes replaced by sequences of simple arithmetic instructions. Examples of (more or less) RISC processors are the {Berkeley RISC}, HP-PA, Clipper, i960, AMD 29000, MIPS R2000 and DEC Alpha. IBM's first RISC computer was the RT/PC (IBM 801), they now produce the RISC-based {RISC System/6000} and SP/2 lines. Despite Apple Computer's bogus claims for their PowerPC-based Macintoshes, the first RISC processor used in a personal computer was the Advanced RISC Machine (ARM) used in the Acorn Archimedes. (1997-06-03)
Reduced instruction set computer         
  • An IBM [[PowerPC 601]] RISC microprocessor
  • RISC-V prototype chip (2013).
PROCESSOR EXECUTING ONE INSTRUCTION IN MINIMAL CLOCK CYCLES
Reduced Instruction Set Computer; RISC processor; Reduced Instruction Set Code; Reduced Instruction Set Computing; RISC; RISC-based; RISC-based system; RISC System/6000 SP; Reduced instruction set; RISC architectures; RISC instruction set; RISC-based computer design approach; RISC principles; Reduced instruction set computing
In computer engineering, a reduced instruction set computer (RISC) is a computer designed to simplify the individual instructions given to the computer to accomplish tasks. Compared to the instructions given to a complex instruction set computer (CISC), a RISC computer might require more instructions (more code) in order to accomplish a task because the individual instructions are written in simpler code.
Orthogonal polynomials         
SET OF POLYNOMIALS WHERE ANY TWO ARE ORTHOGONAL TO EACH OTHER
Orthogonal polynomial; Orthogonal polynomials/Proofs; Orthogonal polynomials/proofs; Orthonormal polynomial
In mathematics, an orthogonal polynomial sequence is a family of polynomials such that any two different polynomials in the sequence are orthogonal to each other under some inner product.
Atmel AVR instruction set         
BKASH
AVR instruction set; Atmel avr instruction set
The Atmel AVR instruction set is the machine language for the Atmel AVR, a modified Harvard architecture 8-bit RISC single chip microcontroller which was developed by Atmel in 1996. The AVR was one of the first microcontroller families to use on-chip flash memory for program storage.
ZISC         
Zero Instruction Set Computer (Reference: CPU)
FMA instruction set         
X86 INSTRUCTION SET EXTENSION DEVELOPED BY INTEL
FMA4 instruction set; FMA3 instruction set; FMA3; FMA4
The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations."FMA3 and FMA4 are not instruction sets, they are individual instructions -- fused multiply add.
instruction set         
  • One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.
SET OF ABSTRACT SYMBOLS (CALLED INSTRUCTIONS) WHICH IDENTIFY AND DESCRIBE OPERATIONS IN A COMPUTER PROGRAM TO A COMPUTER PROCESSOR
Instruction set architectures; Instruction Set Architecture; Instruction Set; Instruction (computer science); Register pressure; Load/store instruction; Load/Store instruction; Electronic action; Zero address machine; Zero-address machine; 0-operand instruction set; Instruction width; Code density; Instruction Sets; Instruction(s) (computer science); Instruction (computing); Native instruction; Variable-length instruction word; Variable-width instruction; Variable width instruction set; Variable width instruction; Variable-width instruction set; Variable length instruction set; Variable length instruction; Variable-length instruction set; Variable-length instruction; Fixed length instruction set; Fixed length instruction; Fixed-length instruction set; Fixed-length instruction; Fixed-width instruction; Fixed-width instruction set; Fixed width instruction; Fixed width instruction set; SIMD instruction; Arithmetic and logic operation; Arithmetic/logic instruction; Load and store instructions; Instruction set; Classification of instruction set architectures
<architecture> The collection of machine language instructions that a particular processor understands. The term is almost synonymous with "{instruction set architecture}" since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate. (1999-07-05)
instruction set architecture         
  • One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.
SET OF ABSTRACT SYMBOLS (CALLED INSTRUCTIONS) WHICH IDENTIFY AND DESCRIBE OPERATIONS IN A COMPUTER PROGRAM TO A COMPUTER PROCESSOR
Instruction set architectures; Instruction Set Architecture; Instruction Set; Instruction (computer science); Register pressure; Load/store instruction; Load/Store instruction; Electronic action; Zero address machine; Zero-address machine; 0-operand instruction set; Instruction width; Code density; Instruction Sets; Instruction(s) (computer science); Instruction (computing); Native instruction; Variable-length instruction word; Variable-width instruction; Variable width instruction set; Variable width instruction; Variable-width instruction set; Variable length instruction set; Variable length instruction; Variable-length instruction set; Variable-length instruction; Fixed length instruction set; Fixed length instruction; Fixed-length instruction set; Fixed-length instruction; Fixed-width instruction; Fixed-width instruction set; Fixed width instruction; Fixed width instruction set; SIMD instruction; Arithmetic and logic operation; Arithmetic/logic instruction; Load and store instructions; Instruction set; Classification of instruction set architectures
<architecture> (ISA) The parts of a processor's design that need to be understood in order to write assembly language, such as the machine language instructions and registers. Parts of the architecture that are left to the implementation, such as number of superscalar functional units, cache size and cycle speed, are not part of the ISA. The definition of SPARC, for example, carefully distinguishes between an implementation and a specification. (1999-01-16)

Википедия

Orthogonal instruction set
In computer engineering, an orthogonal instruction set is an instruction set architecture where all instruction types can use all addressing modes. It is "orthogonal" in the sense that the instruction type and the addressing mode vary independently.